New microprocessors are introduced at such faster and faster pace that it seems a new model of microprocessor is introduced once every two years or even sooner. As capability and/or speed of newly introduced microprocessors frequently surpass older products and as they tend to be more adapted to needs of the market, they are usually more expensive. But when still newer products are introduced, the prices of these once-new products usually drop drastically.
On the other hand, new application software are introduced almost daily which offer more user-friendly and more powerful functions. But these new software typically demand more and more processing power. As a result, users frequently find their computers not powerful enough to run new software one or two years after the purchase thereof. Those given the responsibilities of procuring data processing equipment, and users in general, therefore, face a problem; what computer to purchase and when is the most appropriate time to purchase a new computer.
Basic components of a typical data processing system include a central processing unit (CPU), memories, control circuits (e.g. clock generators) and interface circuits (e.g. bus interface). In most personal computers, the CPU resides in a main processor chip, e.g. the Intel 80.times.86. Because it performs logic and arithmetic functions of the system, the CPU chip is the heart of the system and is a major deciding factor determining a system's capability and performance. If the CPU can be changed, the performance of a system can be improved. It is thus desirable to have a computer that can be upgradeable when new and more powerful microprocessors are introduced.
To make upgrading more economical, the motherboard of some prior art computer systems are modulized so that the CPU and other relevant circuits (e.g. controller circuits) are put onto a special board. The special board can be swapped when a new CPU is introduced. In comparison with buying a whole new computer, upgrading a computer with modulized boards is of course more economical. However, as the associated circuits in the special board still constitute a high percentage of its cost, a substantial waste will still be incurred in upgrading a modulized CPU board.
Modulized CPU boards also take up space, a undesirable result in view of the current demand for smaller and more compact computers.
Currently, the more popular microprocessors used by the industry are the Intel microprocessors model numbers 8086, 80286, 80386 80486 and 80487SX (80487SX, also known as P23N, is a microprocessor having an internal coprocessor). These Intel computers are sometimes referred to as 80.times.86 where x represents a different generation of microprocessors.
Some generations have submodels. For example, the '386 series of microprocessors includes 80386SX (also known as P9) and 80386DX and the '486 series of microprocessors includes 80486DX. Moreover, generation of these computers are also classified in accordance with their respective operation clock frequencies. For example, 80386 has submodels that run on 16 MHz, 20 MHz, 25 MHz and 30 MHz and 80486 has submodels that run on 20 MHz, 25 MHz, 33 MHz and 50 MHz. However, the differences between different generations of microprocessors are usually greater than the differences between submodels.
For a motherboard to be able to operate with different types of CPU, the different characteristics of the different types of CPU must be considered. Also needed to be considered are the specifications of an interface controller (such as the Acer M1209 interface controller) which controls the interface between the CPU and system devices.
In addition, for a motherboard to be able to operate with different types of CPU (e.g. 80486 or 80386), the following technical problems must be considered:
(a) Clock Synchronization
For example, the meaning of "20 MHz" in a model 80386/20 MHz CPU is different from the meaning of "20 MHz" in a model 80486/20 MHz CPU. In a model 80386 CPU, a 40 MHz clock is applied to the CPU chip, and "20 MHz" actually means the frequency of the clock controlling internal operations. For a model 80486 CPU, "20 MHz" means the clock frequency of the external clock applied to the chip. In other words, the frequency of the external clock to the model 80386/20 MHz CPU is actually double that of the model 80486/20 MHz CPU.
Persons skilled in the art know that system clock is commonly divided into different phases and that a certain system activities, such as reading and storing of information, must occur at certain clock phases. For example, in a model 80386 CPU, the cycles of the system clock are divided alternately into a phase 1 and a phase 2. Some system activities, such as the initiation of a CPU cycle (at which time the Address Status signal ADS# is activated) must occur at phase 1, and other system activities, such as reading the CPU Ready signal (CPURDY#) (which signals the end of a CPU cycle) must be performed when phase 2 is changed to phase 1. For 80486 and 80386 to be able to operate in the same motherboard, clock phase problems must be solved.
(b) Signal contention at the system bus
Most CPUs go through initialization before they can begin normal operation. The initialization typically begins when an external signal (for example the CPURST in the 80.times.86 chips) is applied. The external signal causes the CPU to enter into RESET whereby the CPU pins are set to certain levels (i.e. high "1", low "0", floating "F" or undefined).
An external HOLD signal can be applied to cause certain pins of the 80386 to float and electrically isolate from the bus. But some microprocessors such as the 80386 will ignore the HOLD signal at RESET. For other microprocessors such as the 80486, floating pins can be achieved either by applying the HOLD signal or by setting the BOFF# signal to "0" (80386 does not have the BOFF# pin).
For a motherboard to be able to operate when two different types of microprocessors, such as a 80486 and a 80386, are present (so that the system can operate with either one of the two microprocessors), signal contention at the bus must be prevented. Prevention of signal contention can be prevented by performing a power-up sequence to control the CPUs when entering into operation, taking into consideration their respective special characteristics.
(c) Coprocessor interface
Some microprocessor such as the 80386 have a coprocessor (i.e. 80387) which resides in a separate chip. The main processor 80386 must issue a coprocessor cycle in order to communicate with its coprocessor. In other microprocessors such as models 80487SX and 80486DX CPU, the coprocessor is internal to the main processor chip and the main processor of these models of CPU can communicate directly with its internal coprocessor.
In many microprocessor designs, the coprocessor must interface with an interface controller (which provides interface between the CPU and other system components). Different coprocessors interface differently with the interface controller. As a result, the interface signals between a CPU and the interface controller are different (for example, interface signals in the 80486 are Floating Point Error ("FERR#") and Ignore Numeric Error ("IGNNE#"), whereas interface signals in the 80386 are N9BUSY#, N9ERROR# and N9PEREQ ["N9" represents 80387 and "PEREQ" represents COPROCESSOR REQUEST]). Therefore, for an interface controller to be able to work with coprocessors of different microprocessor models, coprocessor interfacing must be provided with the capability to detect and process coprocessor errors of different types of coprocessors.
(d) Different bus sizes and different bus signals
Data addressing by different types of microprocessors is different. For example, 386SX uses a high portion address (A2-A23) to access units of 16 bits of data (a "word") and a low portion address (A0, A1, BHE#) to access either the whole word, the high byte (8 bits) of the word or the low byte (8 bits) of the word; however, 80486 uses the high portion address (A2-A31) to access units of 32 bits of data and the low portion address (BE3#, BE2#, BE1#, BE0#) to determine whether the data to be accessed is the whole 32 bits, or a 24-bit, 16-bit or 8-bit portion thereof.
Moreover, some microprocessor such as the 80486 have an internal cache memory. In such types of microprocessor, a cacheable memory read cycle (also called a cache line full cycle) is used to access 128-bit data from external memory.
Therefore, for a motherboard to be able to use different types of CPU such as either a 80486 or a 80386, bus interfacing must be provided to change and process signals from the different types of CPU.
Accordingly, an object of the invention is to provide a clock synchronization means to handle clock synchronization problems associated with using different types of CPU.
Another object of the invention is to provide a power-up sequencer which prevents signal contention caused by different types of CPU.
Another object of the invention is to provide a coprocessor interface so that coprocessors of different types of CPU can operate with an interface controller which controls other system components.
Another object of the invention is to provide a bus interface which can change and process signals between the system bus and different types of CPU.
Other objects and technical characteristics of the inventions will be understood with reference to the description of the preferred embodiment and the drawings.